A fringe poster session will be scheduled to run parallel to the conference sessions. This is basically open to Master and PhD students and suited for the submissions of original ideas and developments which may not be proven on silicon and hence not ready for a regular conference submission
The posters are to be submitted in the same 4-page format as the regular papers.
The posters are to be submitted by e-mail to email@example.com.
The deadline for poster submission is June 25th.
The size of the poster board is 117 cm (width) x 170 cm (height).
There will be a scheduled Fringe Poster session on Tuesday and Wednesday at
11:00-11:20 during the coffee breaks.
1/D: Sourav Adhikary, High Detectivity(~1011), large
response(~2.2 A/W), Long wavelength (~10.2µm) InGaAs/GaAs quantum dot ...
2/D: Gerhard Landauer, Radiofrequency Performance of Carbon
Nanotube FETs in Comparison to Classical CMOS Technology
4/C: Seulki Lee, A 3-Channel 150mW Electrooculography (EOG)
Monitoring System for Wearable Human Computer Interface(HCI)
5/D: Thomas Holtij, 2D Analytical Modeling of the Potential in
Doped Multiple-Gate-FETs Including Inversion Charge
7/C: Yuri Bocharov, A Low-Power 9-bit Pipelined CMOS ADC with
Amplifier and Comparator Sharing Technique
8/D: Y. T. Kim, Multi-level switching of nano patterned pillar
type phase change memory
10/C: Kazuhiro Takahagi, Low-power Wake-up Receiver With Subthreshold CMOS
Circuits for Wireless Sensor Networks
11/D: F. Mulugeta Yigletu, New Analytical Small Signal HEMT Model
Including Current Collapse Effects for Microwave Simulation
12/C: Loai Salem, Slow-Switching-Limit Loss Removal in SC DC-DC Converters
Using Adiabatic Charging
13/D: A. Malinowski, Development of radical kinetic behaviour
investigation method and its application for sticking coefficient estimation
14/C: Hyunmin Kim, Three Phase Dynamic Current Mode Logic: more secure
DyCML to achieve a more balanced power consumption
16/C: António Couto Pinto, A Flash ADC Tolerant to High Offset Voltage
18/C: Thomas Alpert, A 28 GS/s 6 bit CMOS DAC with Real-Time Interface
19/D: Mike Schwarz, I-V Model for Lightly Doped Schottky Barrier
DG-MOSFETs Including 2D Effects
20/D: Steve Knebel, Impact of high-k metal gate device reliability on
6T-SRAM cell function